Invited Talks

Invited Talks

Shivkumar Kalyanaraman serves as the Chief Scientist of IBM Research – Australia, and is a Senior Technical Staff Member (STSM). Previously he was a Senior Manager of the Next Gen Systems & Smarter Planet Solutions Department at IBM India Research Labs, Bangalore. Prior to this, he was a Manager of the Next Generation Telecom Research group and a Research Staff Member since 2008. Before joining IBM, he was a full Professor at the Department of Electrical, Computer and Systems Engineering at Rensselaer Polytechnic Institute in Troy, NY. He received a B.Tech degree in Computer Science from the Indian Institute of Technology, Madras, India in July 1993, followed by M.S. and Ph.D. degrees at the Ohio State University in 1994 and 1997 respectively. He also holds an Executive M.B.A. (EMBA) degree from Rensselaer Polytechnic Institute (2005). His current research in IBM is at the intersection of emerging wireless technologies and IBM middleware and systems technologies with applications to large-scale smarter planet problems (natural resources, energy, network traffic etc). He was selected by MIT’s Technology Review Magazine in 1999 as one of the top 100 young innovators for the new millenium. He served as the TPC Co-chair of IEEE INFOCOM 2008, and General co-chair of ACM SIGCOMM 2010 in New Delhi. He served on the editorial board of IEEE/ACM Transactions of Networking. He is a Fellow of the IEEE, and an ACM Distinguished Scientist. He is a visiting professor at Universiti Brunei Darussalam, where he co-founded and directs the UBD | IBM Centre, a nationally significant Smarter Planet collaboration between the country of Brunei and IBM.

Dr. Shivkumar Kalyanaraman,
IBM Research

Dr. Venkatarao Ryali,
GE Research

Title: Software Defined Robotics

Abstract: Robots as cyber physical machines embedding intelligent agents capable of performing various tasks with multiple levels of autonomy in interaction with the world around, are witnessing next wave of disruption. Beyond assembly lines they are poised to participate extensively in our home, work and social spaces. Popular technology frameworks like IoT are adopting these machines as sensing and actuation agents in their architectures. When robots need to participate seamlessly in such large systems there is a need for standardization through systematic softwarization and orchestration of sensing, guidance, navigation and manipulation functions. They need to be aware of each other to jointly optimize their resources and operations. Software defined Robotics is conceptualized to address these issues.

Bio: Dr. Balamuralidhar P is a Principal Scientist and Head of TCS Research & Innovation Lab at Tata Consultancy Services Ltd (TCS), Bangalore. He has obtained Bachelor of Technology from Kerala University and Master of Technology (MTech) from IIT Kanpur. His PhD is from Aalborg University, Denmark in the area of Cognitive Wireless Networks. Major areas of current research include different aspects of Cyber Physical Systems, Sensor Informatics & Internet of Things, Robotics & Computer Vision. He has lead several research projects and programs in the above areas.

Dr.Balamuralidhar has over 30 years of research and development experience. He has over 100 publications in various international journals and conferences and over 50 patent filings, out of which 25 have been granted. He is the co-author of a book titled ‘IoT-Technical Challenges and Solutions’ published by Artech Book House. He has co-authored several book chapters and was a guest editor of an International journal on ICT. He has delivered several keynote addresses and invited talks in reputed conferences and symposiums. He is a senior member of IEEE.

Dr. Balamuralidhar,
TCS Innovation Labs

Prof Sudip Misra,
IIT Kharagpur

Dr. Sudip Misra is an Associate Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Kharagpur. Prior to this he was associated with Cornell University (USA), Yale University (USA), Nortel Networks (Canada) and the Government of Ontario (Canada). He received his Ph.D. degree in Computer Science from Carleton University, in Ottawa, Canada. He has several years of experience working in the academia, government, and the private sectors in research, teaching, consulting, project management, architecture, software design and product engineering roles.
His current research interests includes Wireless Ad Hoc and Sensor Networks, Internet of Things (IoT), Software Defined Networks, Cloud Computing, Big Data Networking, Computer Networks, Learning Systems, and algorithm design for emerging communication networks. Dr. Misra is the author of over 260 scholarly research papers, including 150+ reputed journal papers. Dr. Misra has published 9 books in the areas of wireless ad hoc networks, wireless sensor networks, wireless mesh networks, communication networks and distributed systems, network reliability and fault tolerance, and information and coding theory, published by reputed publishers such as Cambridge University Press, Springer, Wiley, and World Scientific.

Title: Intelligent Control of Robotic Systems

Abstract: This talk will cover the development of artificial Intelligence based autonomous  robots. Use of machine learning tools such as self-organising maps, approximate dynamic programming, fuzzy neural networks, and deep learning will be demonstrated in different vision guided robotics applications. Integrating machine intelligence with control theory to ensure stability of such systems will be demonstrated. Some of the interesting applications such as ware-house automation, imitation learning in games, drone assisted driver assistance system and pipeline inspection will be demonstrated. Challenges concerning robotics intelligence based on our research work will be highlighted.

Dr Laxmidhar Behera is working as the Professor at IIT Kanpur having research and teaching experience of more than 23 years. He has received the BSc (engineering) and MSc (engineering) degrees from NIT Rourkela in 1988 and 1990, respectively. He received the PhD degree from IIT Delhi in 1996. He pursued the postdoctoral studies in the German National Research Center for Information Technology, GMD, Sank Augustin, Germany, during 2000-2001. Previously, he has worked as an assistant professor at BITS Pilani during 1995- 1999 and as a reader at Intelligent Systems Research Center (ISRC), University of Ulster, United Kingdom during 2007-2009. He has also worked as a visiting researcher/professor at FHG, Germany, and ETH, Zurich, Switzerland. He is one of the pioneers in the field of AI based autonomous robotics. His work lies in the convergence of machine learning, control theory, robotic vision and heterogeneous robotic platforms. He has received more than INR 15 crore research grants to support his research activities – the recent one being DST-UKIERI International grant. He has established industrial collaboration with TCS, Renault Nissan, and ADNOC, Abu Dhabi while making significant technological development in the areas such robotics based ware-house automation, vision and drone guided driver assistance system, and drone guided pipeline inspection systems. He has published more than 220 papers in Journals and Conference Proceedings. He is a Fellow of INAE and Senior Member of IEEE. His other research interests include intelligent control, semantic signal/music processing, neural networks, control of cyber-physical systems and cognitive modelling.

Prof Laxmidhar Behera,
IIT Kanpur

Harald Gossner

Title: “A different view on robustness of electronic devices in the IoT era”
Classical quality requirements of life time and robustness against large amplitude interferences relate to test methods and targets levels for either a semiconductor (or NEMS/MEMS component) or the final electronic system. In general there is no traceable connection between these tests and test target levels of component and system level such that with increased level of component robustness an increased robustness of the system can be expected. In many cases this has been proven the adverse. Typically supplier and customer learn while refining the design approaches over several generations of products to achieve a stable robustness level. However, in a world of flexible combinations of different electronic base components like sensors and ICs used in completely different applications this can be an expensive hedgehog and hare game. A concept has been developed in ESD design called system efficient ESD design (SEED) which bridges from IC level protection to system level protection. This concept is discussed to show case a fundamental approach for a full understanding of protection design from the semiconductor component to a complete electronic system. This can equally be applied for protection against hard fails as well as for malfunction or soft fails. Developing this idea further can be a hardly overestimated driving force for spreading of IoT applications.

Title: Negative Capacitance Transistors – Physics, Modeling and Processor performance at VDD = 0.4V
The ongoing scaling of CMOS technology is now reaching its limit, due to supply voltage reduction being restricted by the subthreshold swing (SS) of 60mV/decade achievable at room temperature owing to Boltzmann transport of the charge carriers. Concept of negative capacitance proposed to achieve a sub-60mV/decade SS is currently seen as one of the potential solution to the problem. A “negative capacitance transistor (NCFET)” employs a ferroelectric material in the gate stack of a FET providing a negative capacitance and thereby an “internal voltage amplification” at the gate of the internal FET which helps in reducing SS. Several experiments have successfully demonstrated an improved SS with the bulk MOSFET, FinFET, and 2D FETs. The improvement in subthreshold characteristics is also accompanied with the advantage of an increased ON current relative to the reference FET as has been observed both in simulation studies and experiments. In this talk, I will discuss the physics and modeling of various NCFET structures and impact of this new transistor on circuits including processors.

Prof. Yogesh Singh Chauhan

H. S. Jatana

HS Jatana Received his engineering education from BITS Pilani. Worked at AMS Austria for porting of SCL’s CMOS processes at their foundry. Had vast experience on CMOS design, testing, characterization and failure analysis, process development / porting and integration.
Presently, as Group Head at SCL, is responsible for design of VLSI products (ASICS and standard products).
His areas of interest are analog design, development of compatible add-on process options compatible to standard CMOS flow and Process Integration issues in DSM era.
Also interested in spreading VLSI education and have delivered numerous lectures on VLSI at various Institutes.

Title : Engineering Ge and 2D MoS2 transistors for advanced CMOS

Abstract: Germanium has emerged as a strong candidate for replacing Si for future CMOS technologies due to higher carrier mobilities and compatibility with Si processing. However issues such as a poor gate interface, small band-gap, low n-type dopant activation and Fermi-level pinning near the valence band have posed fundamental challenges, especially for realizing high performance n-FETs. This talk will present some of our recent efforts towards engineering high quality gate stacks and low resistance source-drain contacts on Ge through novel processes and materials.

Ultra-thin 2D transition metal dichalcogenides such as MoS2 promise excellent short-channel control for sub-10 nm logic. Recent efforts in our group at reducing contact resistance to MoS2, selectively doping it to realize high performance lateral p-n junctions, and understanding the origins of hysteresis in MoS2 transistors will be discussed.

Bio: Prof. Saurabh Lodha graduated with a B. Tech (EE) from IIT Bombay in 1999 and with a Masters (ECE) and PhD (ECE) from Purdue University in 2001 and 2004 respectively. His graduate research focused on III-V metal/semiconductor interfaces and molecular electronics. From 2005-2010 he worked at Intel Corporation in Portland, USA where he was part of the team responsible for the research and development of 45nm, 32nm and 22nm CMOS technologies. He joined IIT Bombay in July 2010 where his current research interests are in the areas of advanced CMOS, 2D TMD devices and Si photovoltaics.

Prof. Saurabh Lodha

Saravanan Sethuraman

Title: Emerging Memory and Nest Architecture Overview

Abstract: System architects and designers have always wanted more from the memory subsystem with very high performance, high bandwidth, huge capacity, all at minimal or zero cost. Main memory is a critical component and is a fundamental factor in the performance and power consumption of most computing devices. With recent increases in processor core performance and the growing requirements of per core, per thread, bandwidth, efficiency, and predictability out of the memory subsystem make it an even more important and challenging in designing systems. Will the conventional DRAM, Flash memories scaling and IO architecture work for system architects in the future to design a high-performance compute node? What are the alternative emerging memory and nest architectures?

Bio: Saravanan Sethuraman is the Senior Research Engineer focusing on POWER Server Memory Subsystem Development at IBM India Systems Development Lab in Bangalore. He has 18 years of Industry experience which includes system architecture, design & development leading to volume manufacturing. He is currently focusing on the next generation memory subsystem architecture for the upcoming IBM’s high-performance compute nodes. He is a JEDEC member working to define DDR4, 3DS and future memory technology standards. He is appointed as IBM Master Inventor with 100+ patents/applications and published papers in IEEE conferences in future memory architectures and reliability. He is serving as vice-chairman for IEEE Solid State Circuits and Electron Devices Society, Bangalore chapter and a IEEE Senior member. He has received his MS degree from BITS-Pilani and is a member of IBM India Technical Experts Council affiliated by IBM Academy of Technology.

Title-Hardware design challenges for next generation computing

Abstract: The talk focusses around current hardware design life cycle, discussions around critical drivers for design process changes, where are the key gaps etc. The talk invokes thoughts around how the engineering community may come together to address these gaps.

Bio: Parthasarathy Ramaswamy (Partha) 20 years of industry experience in the area of High speed Signaling and power delivery- Currently a principal Engineer at Intel Server engineering division leading Signal and power integrity teams. Partha has a Ph.D. in electromagnetics and has many patents filed/granted and publications in this area.

Parthasarathy Ramaswamy

Dr. Amith Singhee


Title-Al at the Edge and Related Topics

Dr. Amith Singhee is a Manager and Senior Technical Staff Member at IBM Research, India. He leads the research agenda for Industry Solutions in the sectors of Retail, Distribution and Buildings. From 2008 to 2015, he was with the IBM T. J. Watson Research Center in NY, USA. He has extensive experience in applying artificial intelligence, IoT, enterprise architecture, Cloud and mobile to real-world business processes across multiple sectors such as energy, agriculture, buildings and retail. He has worked with large power utilities in the US to develop solutions for improved storm preparation and response using data analytics, machine learning, customized weather forecasting and optimization. He led an effort to develop a big-data analytics platform for developing and deploying a wide array of analytics-driven solutions for asset-heavy industries like energy and utilities, telecom, etc. This led to multiple new product offerings from IBM. In the past he has also worked for many years in electronic design automation, particularly in design optimization, simulation, modeling and design methodologies in the presence of environmental and manufacturing variability. As part of his work at IBM Research he led the effort to define a new methodology for SRAM technology development at advanced IC manufacturing technology nodes.

From 2002 to 2004, Amith was at Neolinear, Inc, and subsequently Cadence Design Systems, where he was the lead developer of the circuit optimization engine in the NeoCircuit tool, and developed new methods for stochastic optimization of analog circuits and automated design of hierarchical, system-level designs.

Amith has a PhD in Electrical and Computer Engineering from Carnegie Mellon University. He is a winner of several awards, specifically the Donald O. Pederson award from IEEE/CEDA, the Outstanding Dissertation Award from EDAA, the Arthur G. Milnes Award from Carnegie Mellon University, and best paper awards at top Power and EDA conferences, such as IEEE PES General Meeting, DAC, DATE and VLSI Design. He is a Senior Member of the IEEE and a member of the ACM.


Bio: He is the Infosys Foundation Chair Professor at IIIT Bangalore and co-founder and CEO of VideoKen, an educational technology startup. Served as Vice President and Director of Xerox Research Center India (XRCI)  from 2013-2016, helping build XRCI into a world class research center. Earlier helped take IBM Research – India to a high level of impact on IBM business (recognized internally through a record number of IBM Research Division Accomplishments) and significant external recognition (13 best paper awards at international conferences during my tenure of four years). Led research at IBM T.J. Watson Research Center on system software for the Blue Gene supercomputer, for which IBM received the National Medal of Technology and Innovation in 2009 from the US President, and other Deep Computing platforms. Has received an Outstanding Innovation Award, two Outstanding Technical Achievement Awards, and the Lou Gerstner Award for Client Excellence at IBM. He has co-authored about 75 papers in the areas of parallel computing, high performance compilers, and Java Virtual Machine optimizations, with over 6,000 citations in Google Scholar and an h-index of 42, and has been granted 19 US patents. He has served on the US National Science Foundation Committee of Visitors and has been invited to give keynotes at several international conferences like ICSOC, IPDPS, DEBS and HiPC. Currently serving as Chair of IKDD, the ACM India Chapter for Knowledge Discovery and Data Mining.  He is an ACM Fellow, a Fellow of the Indian National Academy of Engineering, and have received a Distinguished Alumnus Award from Indian Institute of Technology, Delhi.


Dr. Manish Gupta

Dr. Arpita Patra


The focus of my research is the theoretical foundations of cryptography that are concerned Research Interests with the feasibility of securely realizing cryptographic tasks, finding inherent lower bounds on the computational resources that are needed for solving cryptographic tasks and finding resource efficient secure constructions. The resources most often considered are computational complexity (i.e., measuring the time required to compute some cryptographic function like encryption or secure computation of a functionality), round and communication complexity (i.e., the number of rounds and bandwidth required for a secure interactive protocol). The topics of cryptography I have been interested in so far include: Secure Communication, Secure Multiparty Computation, Verifiable Secret Sharing, Adaptive Security, Public Key Encryption, Oblivious Transfer, Zero Knowledge Proofs, Byzantine Agreement and Broadcast.



Areas of research and specialization include High Performance Computing clustered systems, with an emphasis on fault tolerance, checkpoint and recovery schemes; and HPC file systems. In the recent past, I worked on applications of Semantic Web technologies in enterprise applications. Current work is in the area of automated IT infrastructure provisioning with an attempt to marry some of the HP Labs technologies with HP Enterprise Management Software products and solutions, including cloud-ready infrastructure solutions.



Dr. Badrinath Ramamurthy